US 11,994,990 B2
Memory media row activation-biased caching
Edmund Gieske, Boise, ID (US); and Cagdas Dirik, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 9, 2022, as Appl. No. 17/941,558.
Claims priority of provisional application 63/301,991, filed on Jan. 21, 2022.
Prior Publication US 2023/0236968 A1, Jul. 27, 2023
Int. Cl. G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/1032 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A cache memory comprising:
a plurality of cache lines;
row activation status memory comprising a row activation status associated with each of the plurality of cache lines, the row activation status of each cache line indicating information of a volume of accesses in a memory media device to a row corresponding to said each cache line; and
a control circuitry configured to perform operations comprising, in response to a request to store data in the plurality of cache lines, at least one of:
determining, based at least on said information of the volume of accesses to a row associated with the data, whether or not to store the data in at least one cache line in the plurality of cache lines; and
selecting, based at least on said row activation status of the plurality of cache lines, a cache line to be evicted; and
wherein the row activation status comprises a bit indicating a row hammer status, wherein when the bit is set, the control circuitry is configured to bias the corresponding cache line against eviction.