US 11,994,948 B2
Semiconductor memory devices, memory systems including the same and methods of operating memory systems
Hoi-Ju Chung, Yongin-si (KR); Sang-Uhn Cha, Yongin-si (KR); Ho-Young Song, Hwaseong-si (KR); and Hyun-Joong Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 3, 2023, as Appl. No. 18/164,349.
Application 18/164,349 is a continuation of application No. 17/562,505, filed on Dec. 27, 2021, granted, now 11,593,199.
Application 17/562,505 is a continuation of application No. 17/137,535, filed on Dec. 30, 2020, granted, now 11,231,996, issued on Jan. 25, 2022.
Application 17/137,535 is a continuation of application No. 16/894,115, filed on Jun. 5, 2020, granted, now 10,929,225, issued on Feb. 23, 2021.
Application 16/894,115 is a continuation of application No. 16/015,534, filed on Jun. 22, 2018, granted, now 10,705,908, issued on Jul. 7, 2020.
Application 16/015,534 is a continuation of application No. 15/238,216, filed on Aug. 16, 2016, granted, now 10,037,244, issued on Jul. 31, 2018.
Claims priority of application No. 10-2015-0160106 (KR), filed on Nov. 16, 2015.
Prior Publication US 2023/0185664 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G11C 29/52 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 29/70 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array including a plurality of memory cells;
a controller configured to control at least two operations, each of the at least two operations including access to the memory array; and
a counter configured to generate an address for accessing memory cell rows in the memory array under control of the controller,
wherein the controller is configured to perform an error check and correction (ECC) decoding sequentially on data stored in the plurality of memory cells designated by the address in response to the controller receiving a command among a plurality of commands,
wherein the controller is configured to correct the data when the ECC decoding indicates the data includes at least one error bit and output the corrected data to a memory controller, when the command designates a normal mode, and
wherein the controller is configured to correct the data when the ECC decoding indicates the data includes at least one error bit, and write back the corrected data to the memory array, when the command designates an error check and scrub (ECS) mode.