US 11,994,945 B2
Managing write disturb for units of memory in a memory sub-system
Zhenming Zhou, San Jose, CA (US); Tingjun Xie, Milpitas, CA (US); and Charles See Yeung Kwong, Redwood City, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 6, 2023, as Appl. No. 18/296,595.
Application 18/296,595 is a continuation of application No. 17/467,826, filed on Sep. 7, 2021, granted, now 11,656,936.
Prior Publication US 2023/0244566 A1, Aug. 3, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/106 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method comprising:
determining that a value of a write counter associated with a memory device satisfies a first threshold criterion, wherein the write counter is a global counter indicating a number of write operations to the memory device;
determining that a set of failed bit count statistics corresponding to a plurality of codewords of a memory unit of the memory device satisfies a second threshold criterion; and
responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the memory unit satisfies the second threshold criterion, performing a write scrub operation on the memory unit.