US 11,994,943 B2
Configurable data path for memory modules
Thomas H. Kinsley, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jul. 29, 2022, as Appl. No. 17/877,706.
Application 17/877,706 is a continuation of application No. 16/715,183, filed on Dec. 16, 2019, granted, now 11,403,238.
Claims priority of provisional application 62/787,039, filed on Dec. 31, 2018.
Prior Publication US 2023/0032668 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1068 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array;
an input/output circuit coupled to the memory array and configured to input or output a plurality of data nibbles based on a plurality of data strobe signals;
a mode register configured to store a plurality of bits, each bit indicating for a corresponding one of the plurality of data nibbles whether a cyclic redundancy check (CRC) is enabled; and
an error controller configured to generate a CRC code for each of the plurality of data nibbles for which the corresponding bit of the plurality of bits indicates that the CRC is enabled.