US 11,994,936 B2
Automated optimization of error-handling flows in memory devices
Jay Sarkar, San Jose, CA (US); Ipsita Ghosh, Kolkata (IN); and Vamsi Pavan Rayaprolu, Santa Clara, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/897,910.
Prior Publication US 2024/0070008 A1, Feb. 29, 2024
Int. Cl. G06F 11/07 (2006.01)
CPC G06F 11/0784 (2013.01) [G06F 11/0757 (2013.01); G06F 11/0787 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A host system comprising:
a memory; and
a processing device, operatively coupled to the memory, to perform operations comprising:
receiving, by the host system, from a memory sub-system operatively coupled to the host system, log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device of the memory sub-system;
applying, by the host system, an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and
responsive to applying the optimization model to the log data, obtaining, by the host system, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.