US 11,994,932 B2
Platform ambient data management schemes for tiered architectures
Karthik Kumar, Chandler, AZ (US); Thomas Willhalm, Sandhausen (DE); and Francesc Guim Bernat, Barcelona (ES)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 21, 2020, as Appl. No. 16/907,264.
Prior Publication US 2020/0319696 A1, Oct. 8, 2020
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3287 (2013.01)] 23 Claims
OG exemplary drawing
 
10. A platform, comprising:
one or more central processing units (CPUs);
a plurality of Dual Inline Memory Modules (DIMMs), operatively coupled to the one or more CPUs, wherein the plurality of DIMMS is implemented in a plurality of memory tiers including a first tier and a second tier;
at least one of embedded logic and embedded hardware configured to,
copy data from one or more DIMMs in the first tier to one or more DIMMs in the second tier; and
put the one or more DIMMs in the first tier from which data were copied into a reduced power or deactivated state,
wherein the at least one of embedded logic and embedded hardware includes one or more embedded processing elements and at least one of software and firmware instructions configured to be executed on the one or more embedded processing elements.