US 11,994,559 B2
Tests for integrated circuit (IC) chips
Lakshmanan Balasubramanian, Bangalore (IN); Rubin Parekhji, Bangalore (IN); Kalyan Chakravarthi Chekuri, Bangalore (IN); and Swathi G, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 22, 2022, as Appl. No. 17/871,205.
Claims priority of application No. 202141051160 (IN), filed on Nov. 8, 2021.
Prior Publication US 2023/0143500 A1, May 11, 2023
Int. Cl. G01R 31/3183 (2006.01); G06F 30/30 (2020.01)
CPC G01R 31/31835 (2013.01) [G01R 31/318307 (2013.01); G01R 31/318357 (2013.01); G06F 30/30 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for evaluating tests for fabricated integrated circuit (IC) chips comprising:
providing, by an IC fault engine operating on a computing platform, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design;
fault simulating, by an analog fault simulator (AFS) operating on the computing platform, the IC design and a corresponding identified test suite to determine a signature for faults;
simulating, by a circuit simulator operating on the computing platform, the IC design with the DfFI instances activated to determine a signature for the DfFI instances;
generating, by the IC fault engine, a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and the signatures of the DfFI instances;
generating and/or managing, by an IC test engine operating on the computing platform, tests for a fabricated IC chip that is based on the IC design;
receiving, by the IC test engine, test result data that characterizes the tests being applied against the fabricated IC chip based on the IC design with the DfFI instances activated; and
analyzing, by the IC test engine, the test result data to determine an ability of the tests to detect the faults.