| CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] | 24 Claims |

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1. A semiconductor structure comprising:
a magnetic tunnel junction, the magnetic tunnel junction having a first magnetic layer and a second magnetic layer separated by a tunnel layer;
a hard mask cap above the second magnetic layer, wherein a width of the hard mask cap is less than a width of the second magnetic layer;
a first encapsulation spacer positioned along and directly contacting vertical sidewalls of the hard mask cap, wherein a top surface of the first encapsulation spacer is flush with a top surface of the hard mask cap;
a second encapsulation spacer positioned along and directly contacting vertical sidewalls of the second magnetic layer, wherein a top surface of the second encapsulation spacer is flush with the top surface of the hard mask cap;
a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, wherein a top surface of the third encapsulation spacer is flush with the top surface of the hard mask cap;
a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer, wherein a top surface of the fourth encapsulation spacer is flush with the top surface of the hard mask cap;
a first metal interconnect above the hard mask cap; and
a barrier layer separating upper surfaces of each of the first encapsulation spacer, second encapsulation spacer, third encapsulation spacer, and fourth encapsulation spacer from the first metal interconnect.
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