US 12,317,627 B2
Semiconductor apparatus and semiconductor apparatus manufacturing method
Tadashi Iijima, Kanagawa (JP); and Yuki Miyanami, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/619,750
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jun. 26, 2020, PCT No. PCT/JP2020/025145
§ 371(c)(1), (2) Date Dec. 16, 2021,
PCT Pub. No. WO2020/262582, PCT Pub. Date Dec. 30, 2020.
Claims priority of application No. 2019-119166 (JP), filed on Jun. 26, 2019.
Prior Publication US 2022/0359599 A1, Nov. 10, 2022
Int. Cl. H10F 39/00 (2025.01); H01L 23/00 (2006.01)
CPC H10F 39/809 (2025.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H10F 39/018 (2025.01); H10F 39/811 (2025.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor apparatus, comprising:
a first substrate that includes:
a first element layer including a first active element; and
a first wiring layer on the first element layer; and
a second substrate that includes:
a second element layer including a second active element on the first wiring layer, wherein the second element layer includes a first compound semiconductor substrate; and
a second wiring layer on the second element layer, wherein
the second element layer is between the first wiring layer and the second wiring layer,
the first substrate is on the second substrate,
the second active element includes a transistor, and
a source region and a drain region of the second active element are in the first compound semiconductor substrate.