US 12,317,622 B2
Pixel array providing flicker reduction and dynamic range
Chun-Lin Fang, Tainan (TW); Ping-Hao Lin, Tainan (TW); and Kuo-Cheng Lee, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd, Hsinchu (TW)
Filed on Nov. 20, 2020, as Appl. No. 16/949,928.
Prior Publication US 2022/0165771 A1, May 26, 2022
Int. Cl. H10F 39/00 (2025.01)
CPC H10F 39/8057 (2025.01) [H10F 39/024 (2025.01); H10F 39/807 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A pixel array, comprising:
a plurality of pixel regions, of a substrate, including a first pixel region, a second pixel region, and a third pixel region;
a dielectric liner on a surface of the substrate and on a surface of each of a plurality of openings in the substrate, wherein each of the plurality of openings comprises angled sidewalls;
a plurality of deep trench isolation (DTI) elements, in the plurality of openings and on the dielectric liner, including:
a first DTI element adjacent to a first side of the first pixel region, and
a second DTI element between a second side of the first pixel region and the second pixel region or between the second pixel region and the third pixel region;
a buffer layer over the plurality of pixel regions and the plurality of DTI elements, wherein the buffer layer comprises a first material and the plurality of DTI elements comprises a second material different from the first material;
a metal grid structure, over the plurality of pixel regions and the buffer layer, comprising angled sidewalls configured to direct incoming light to one of the plurality of pixel regions, wherein the angled sidewalls of the metal grid structure reside above, and are at an opposite angle from, the angled sidewalls of the plurality of openings;
an oxide layer over, and in direct contact with, the metal grid structure and the buffer layer, wherein the oxide layer comprises a first portion residing on a top surface of the metal grid structure and a second portion residing on a top surface of the buffer layer, wherein a top surface of the first portion resides above a top surface of the second portion; and
a light blocking layer,
a first portion of the light blocking layer being over the first pixel region and under the metal grid structure, the first portion having a first thickness; and
a second portion of the light blocking layer being over the third pixel region and having a second thickness that is different from the first thickness.