US 12,317,611 B2
Photoelectric conversion element and photoelectric conversion device
Hiroshi Sekine, Kanagawa (JP)
Assigned to CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Nov. 1, 2022, as Appl. No. 18/051,677.
Claims priority of application No. 2021-191170 (JP), filed on Nov. 25, 2021.
Prior Publication US 2023/0163229 A1, May 25, 2023
Int. Cl. H10F 30/222 (2025.01); H10F 30/225 (2025.01); H10F 77/20 (2025.01); H10F 77/40 (2025.01)
CPC H10F 30/222 (2025.01) [H10F 30/225 (2025.01); H10F 77/206 (2025.01); H10F 77/413 (2025.01)] 22 Claims
OG exemplary drawing
 
1. A photoelectric conversion element provided in a semiconductor layer having a first surface and a second surface opposed to the first surface comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type disposed closer to the second surface than the first semiconductor region and forming a p-n junction with the first semiconductor region;
a third semiconductor region of the first conductivity type disposed closer to the second surface than the second semiconductor region and overlapping with the first semiconductor region and the second semiconductor region in a plan view;
a fourth semiconductor region of the second conductivity type disposed closer to the second surface than the third semiconductor region and overlapping with the whole of a region where the first semiconductor region, the second semiconductor region, and the third semiconductor region are disposed in the plan view;
a fifth semiconductor region of the second conductivity type disposed at a depth between the third semiconductor region and the fourth semiconductor region; and
a sixth semiconductor region of the second conductivity type disposed so as to surround a region where the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fifth semiconductor region are disposed in the plan view, and electrically connected to the fourth semiconductor region,
wherein the fifth semiconductor region has an area smaller than an area of the third semiconductor region in the plan view and overlaps with the first semiconductor region in the plan view.