US 12,317,601 B2
Dual-port SRAM structure
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 12, 2024, as Appl. No. 18/439,486.
Application 18/439,486 is a continuation of application No. 17/811,260, filed on Jul. 7, 2022, granted, now 11,901,352.
Application 17/811,260 is a continuation of application No. 16/932,394, filed on Jul. 17, 2020, granted, now 11,444,072, issued on Sep. 13, 2022.
Claims priority of provisional application 62/981,317, filed on Feb. 25, 2020.
Prior Publication US 2024/0186311 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 89/10 (2025.01); H10B 10/00 (2023.01); H10D 84/85 (2025.01)
CPC H10D 89/10 (2025.01) [H10B 10/12 (2023.02); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A static random access memory (SRAM) array, comprising:
a plurality of memory cells, each of the plurality of memory cells comprising:
a first active region and a second active region disposed over an n-well and extending along a first direction;
a third active region and a fourth active region disposed over a first p-well abutting the n-well and extending along the first direction;
a fifth active region and a sixth active region disposed over a second p-well abutting the n-well and extending along the first direction;
a first gate structure extending along a second direction perpendicular to the first direction to wrap over the third active region, the fourth active region, and the first active region; and
a second gate structure extending along the second direction to wrap over the second active region, the fifth active region, and the sixth active region,
wherein the first p-well and the second p-well sandwiches the n-well along the second direction.