| CPC H10D 62/021 (2025.01) [H01L 21/3065 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01)] | 20 Claims |
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1. A method comprising:
forming a semiconductor structure that extends from a substrate along a first direction, wherein the semiconductor structure has a height along the first direction and the semiconductor structure extends lengthwise along a second direction that is different than the first direction;
forming a gate structure over a first region of the semiconductor structure, wherein the gate structure extends lengthwise along a third direction that is different than the second direction, the gate structure includes a gate stack and gate spacers, and the gate spacers are disposed along sidewalls of the gate stack;
forming a source/drain trench in a second region of the semiconductor structure by:
performing a first anisotropic etch to provide the source/drain trench with a first depth along the first direction,
performing an isotropic etch that enlarges the source/drain trench along the second direction, wherein the isotropic etch extends the source/drain trench under one of the gate spacers and the isotropic etch implements a fluorine-and-chlorine-containing etch gas, and
performing a second anisotropic etch to extend the source/drain trench to a second depth along the first direction, wherein each of the first anisotropic etch and the second anisotropic etch implement a hydrogen-and-bromine-containing etch gas; and
forming an epitaxial semiconductor structure in the source/drain trench in the second region of the semiconductor structure, wherein the second region is adjacent to the first region.
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