US 12,317,517 B2
Semiconductor die package and methods of formation
Shu-Hui Su, Tucheng (TW); Hsin-Li Cheng, Hsin Chu (TW); and YingKit Felix Tsui, Cupertino, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 6, 2023, as Appl. No. 18/151,059.
Claims priority of provisional application 63/377,648, filed on Sep. 29, 2022.
Prior Publication US 2024/0113159 A1, Apr. 4, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/60 (2006.01); H01L 25/16 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 80/30 (2025.01)
CPC H10D 1/042 (2025.01) [H01L 23/5223 (2013.01); H01L 23/60 (2013.01); H01L 24/04 (2013.01); H01L 24/80 (2013.01); H10D 1/716 (2025.01); H01L 2224/04105 (2013.01); H01L 2224/80895 (2013.01); H01L 2924/19041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor die package, comprising:
a first semiconductor die, comprising:
a first device region that includes a first decoupling trench capacitor region including a first decoupling trench capacitor structure and a second decoupling trench capacitor region including a second decoupling trench capacitor structure,
wherein a first height of the first decoupling trench capacitor structure in the first decoupling trench capacitor region, and a second height of a second decoupling trench capacitor structures in the second decoupling capacitor region, are different heights; and
a first interconnect region vertically adjacent to the first device region at a first side of the first interconnect region and including a plurality of metallization layers that are electrically connected with the first and second decoupling trench capacitor structures; and
a second semiconductor die, bonded with the first semiconductor die at a second side of the first interconnect region opposing the first side, comprising:
a second device region including one or more semiconductor devices; and
a second interconnect region vertically adjacent to the second device region.
 
10. A method, comprising:
forming a plurality of decoupling trench capacitor regions in a device region of a first semiconductor die,
wherein a first plurality of decoupling trench capacitor structures, of a first decoupling trench capacitor region of the plurality of decoupling trench capacitor regions, are formed to a first depth in the device region,
wherein a second plurality of decoupling trench capacitor structures, of a second decoupling trench capacitor region of the plurality of decoupling trench capacitor regions, are formed to a second depth in the device region, and
wherein the first depth and the second depth are different depths relative to a surface of the device region;
forming an interconnect region over the device region after forming the plurality of decoupling trench capacitor regions; and
bonding the first semiconductor die with a second semiconductor die at a bonding interface.
 
17. A semiconductor die package, comprising:
a first semiconductor die, comprising:
a first device region that includes a first decoupling trench capacitor region including a first decoupling trench capacitor structure and a second decoupling trench capacitor region including a second decoupling trench capacitor structure;
a first interconnect region vertically adjacent to the first device region at a first side of the first interconnect region;
a second semiconductor die, bonded with the first semiconductor die at a second side of the first interconnect region opposing the first side, comprising:
a second device region including:
one or more semiconductor devices; and
an electrostatic discharge (ESD) protection circuit; and
a second interconnect region vertically adjacent to the second device region; and
a seal ring structure that extends through the first interconnect region and the second interconnect region,
wherein the seal ring structure electrically connects the ESD protection circuit with the first and second decoupling trench capacitor structures.