| CPC H10D 1/042 (2025.01) [H10B 43/40 (2023.02); H10D 1/043 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01); H10B 43/27 (2023.02)] | 14 Claims |
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1. A semiconductor device comprising:
a stack including a plurality of electrode layers that include a plurality of capacitor first electrode layers and a plurality of capacitor second electrode layers alternately stacked on a substrate and a plurality of dielectric layers which are disposed between the capacitor first electrode layers and the capacitor second electrode layers;
a first conductive pillar passing through the stack and coupled to the plurality of capacitor first electrode layers;
a second conductive pillar passing through the stack and coupled to the plurality of capacitor second electrode layers; and
a plurality of insulation layer patterns insulating the first conductive pillar and the plurality of capacitor second electrode layers from each other and insulating the second conductive pillar and the plurality of capacitor first electrode layers from each other,
wherein an outer wall of the first conductive pillar is not surrounded by the plurality of insulation layer patterns at the same layers as the plurality of capacitor first electrode layers,
wherein the plurality of capacitor first electrode layers are in contact with the outer wall of the first conductive pillar,
wherein an outer wall of the second conductive pillar is not surrounded by the plurality of insulation layer patterns at the same layers as the plurality of capacitor second electrode layers,
wherein the plurality of capacitor second electrode layers are in contact with the outer wall of the second conductive pillar.
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