US 12,317,490 B2
Semiconductor memory device
Akira Yotsumoto, Yokkaichi (JP); Keisuke Suda, Yokkaichi (JP); Kenji Tashiro, Kuwana (JP); Tetsuya Yamashita, Yokkaichi (JP); and Daigo Ichinose, Nagoya (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 14, 2022, as Appl. No. 17/693,617.
Claims priority of application No. 2021-152448 (JP), filed on Sep. 17, 2021.
Prior Publication US 2023/0086773 A1, Mar. 23, 2023
Int. Cl. H10B 43/10 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/10 (2023.02) [H10B 41/41 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a stacked body having a stacked structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a dummy region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers, the dummy region including a first stepped portion in which at least a part of the plurality of conductive layers on an upper layer side is processed in a stepped shape and terminates at an end portion opposite to the memory region in the first direction;
a plurality of first pillars extending in the stacked body in the stacking direction in the memory region and each forming memory cells at respective intersections with at least a part of the plurality of conductive layers; and
first and second plate-like portions extending in the stacking direction and the first direction in the stacked body at positions in the memory region away from each other in a second direction intersecting the stacking direction and the first direction, the first and second plate-like portions being directly or indirectly connected to each other and terminating in the dummy region, each of the first and second plate-like portions dividing the stacked body excluding at least a part of the end portion of the dummy region in the second direction, wherein
the memory region includes:
a first memory region; and
a second memory region arranged at a position away from the first memory region in the first direction,
the stacked body includes a second stepped portion in which the plurality of conductive layers is processed in a stepped shape and that extends in the first direction at a position between the first and second memory regions, and
the first plate-like portion extends in the first direction outside the second stepped portion in the second direction.