US 12,317,470 B2
Semiconductor device, semiconductor structure and formation method thereof
Ping-Heng Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Oct. 28, 2021, as Appl. No. 17/452,614.
Application 17/452,614 is a continuation of application No. PCT/CN2021/106693, filed on Jul. 6, 2021.
Prior Publication US 2022/0122987 A1, Apr. 21, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/038 (2023.02) [H10B 12/37 (2023.02); H10B 12/482 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor structure formation method, comprising:
providing a substrate, and forming a sacrificial layer on the substrate;
patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer, wherein a plurality of the through holes are distributed between adjacent two of trenches, and the plurality of the through holes spaced along an extension direction of the trenches;
forming insulating layers covering a sidewall of each of the trenches and a sidewall of each of the through holes;
sequentially forming a conductive layer and a passivation layer in each of the trenches and each of the through holes to form a bitline structure in each of the trenches and a capacitor contact structure in each of the through holes simultaneously, wherein a top surface of the passivation layer being flush with a top surface of the sacrificial layer;
removing the passivation layer in each of the through holes to form a expose the capacitor contact structure in each of the through holes; and
forming a capacitor in a contact connection with the capacitor contact structure.