US 12,317,469 B2
Semiconductor device
Shunpei Yamazaki, Tokyo (JP); Hiroki Komagata, Kanagawa (JP); Yoshihiro Komatsu, Kanagawa (JP); Shinya Sasagawa, Kanagawa (JP); Takashi Hamada, Kanagawa (JP); Yasumasa Yamane, Kanagawa (JP); and Shota Mizukami, Hokkai-do (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 17/773,068
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Oct. 29, 2020, PCT No. PCT/IB2020/060123
§ 371(c)(1), (2) Date Apr. 29, 2022,
PCT Pub. No. WO2021/090115, PCT Pub. Date May 14, 2021.
Claims priority of application No. 2019-203249 (JP), filed on Nov. 8, 2019; and application No. 2019-203250 (JP), filed on Nov. 8, 2019.
Prior Publication US 2022/0399338 A1, Dec. 15, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01)
CPC H10B 12/00 (2023.02) [H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit region and a second circuit region over a substrate,
wherein the first circuit region comprises:
a plurality of first transistors; and
a first insulator over the plurality of first transistors,
wherein the second circuit region comprises:
a plurality of second transistors; and
a second insulator over the plurality of second transistors,
wherein the second insulator includes an opening portion,
wherein the first transistors and the second transistors each include an oxide semiconductor,
wherein a third insulator is positioned over and in contact with the first insulator and the second insulator, and
wherein density of the plurality of first transistors arranged in the first circuit region is higher than density of the plurality of second transistors arranged in the second circuit region.