| CPC H10B 10/12 (2023.02) [C01G 23/0536 (2013.01); H01L 23/535 (2013.01); H10B 12/033 (2023.02); H10B 12/0385 (2023.02); H10B 12/09 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10D 62/221 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); C01P 2004/52 (2013.01); C01P 2004/62 (2013.01); C01P 2004/64 (2013.01); C01P 2006/12 (2013.01); H10D 84/0177 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
an element isolation layer on the boundary region of the substrate;
a dielectric layer on the boundary region and the core region of the substrate; and
a gate structure including a first conductive pattern, a second conductive pattern, and a third conductive pattern, the first conductive pattern on the dielectric layer and including a first extension portion on the boundary region of the substrate, the second conductive pattern on and directly in contact with the first conductive pattern and including a second extension portion on the boundary region of the substrate, the third conductive pattern on and directly in contact with the second conductive pattern and including a third extension portion on the boundary region of the substrate,
wherein a length of the second extension portion of the second conductive pattern is greater than a length of the first extension portion of the first conductive pattern, and is less than a length of the third extension portion of the third conductive pattern, and
the third extension portion of the third conductive pattern directly contacts the element isolation layer.
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