US 12,316,991 B2
Imaging device and electronic device
Shunpei Yamazaki, Tokyo (JP); and Takayuki Ikeda, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jul. 8, 2024, as Appl. No. 18/766,024.
Application 18/766,024 is a continuation of application No. 17/422,580, granted, now 12,035,061, issued on Jul. 9, 2024, previously published as PCT/IB2020/050457, filed on Jan. 22, 2020.
Claims priority of application No. 2019-013507 (JP), filed on Jan. 29, 2019.
Prior Publication US 2024/0365021 A1, Oct. 31, 2024
Int. Cl. H04N 25/75 (2023.01); H04N 25/79 (2023.01); H10F 39/00 (2025.01)
CPC H04N 25/75 (2023.01) [H04N 25/79 (2023.01); H10F 39/8037 (2025.01); H10F 39/811 (2025.01)] 9 Claims
OG exemplary drawing
 
1. An imaging device comprising:
a photoelectric conversion device; and
a memory device,
wherein the memory device comprises:
a first transistor;
a second transistor;
a third transistor; and
a capacitor,
wherein a channel formation region of the first transistor comprises silicon,
wherein a first insulator is provided over the channel formation region of the first transistor,
wherein a first gate of the first transistor is provided over the first insulator,
wherein a second insulator is provided over the first gate of the first transistor,
wherein a second gate of the second transistor and a third gate of the third transistor are provided over the second insulator,
wherein a third insulator is provided over the second gate of the second transistor and the third gate of the third transistor,
wherein a first oxide and a second oxide are provided over the third insulator,
wherein the first oxide comprises a channel formation region of the second transistor,
wherein the second oxide comprises a channel formation region of the third transistor,
wherein a fourth gate of the second transistor is provided over the first oxide,
wherein a fifth gate of the third transistor is provided over the second oxide, and
wherein the second gate of the second transistor is electrically connected to the third gate of the third transistor, the fifth gate of the third transistor, and a source of the third transistor.