| CPC H04N 23/80 (2023.01) [H04N 23/73 (2023.01)] | 20 Claims |

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1. A method for on-the-fly camera image processing, comprising:
configuring, by a first processing circuit in a system-on-chip (SoC), one or more synchronization settings in a configuration register memory;
processing, by an image signal processing (ISP) pipeline that is connected in the SoC and that is configured by a first synchronization setting having a first value, first and second camera image frame sequences having, respectively, first and second specified exposures to detect a set of complete frames from the first and second camera image frame sequences which have a first common frame number;
identifying, by the ISP pipeline, a valid combination of different exposures from the first and second camera image frame sequences having a second common frame number succeeding the first common frame number; and
processing, by the ISP pipeline, the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.
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