US 12,316,727 B2
Device and computing system including the device
Yong Tae Jeon, Icheon-si (KR); Dae Sik Park, Icheon-si (KR); Jae Young Jang, Icheon-si (KR); Byung Cheol Kang, Icheon-si (KR); and Seung Duk Cho, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 11, 2023, as Appl. No. 18/350,220.
Application 17/840,340 is a division of application No. 17/349,775, filed on Jun. 16, 2021, granted, now 11,546,128, issued on Jan. 3, 2023.
Application 18/350,220 is a continuation of application No. 17/840,340, filed on Jun. 14, 2022.
Claims priority of application No. 10-2020-0073157 (KR), filed on Jun. 16, 2020; application No. 10-2021-0042642 (KR), filed on Apr. 1, 2021; and application No. 10-2021-0044151 (KR), filed on Apr. 5, 2021.
Prior Publication US 2023/0353341 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04L 25/00 (2006.01)
CPC H04L 7/005 (2013.01) [H04L 7/0079 (2013.01); H04L 7/0091 (2013.01); H04L 7/033 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a first interface device including a first buffer and structured to be operable to be in communication with a second interface device including a second buffer, the method comprising:
initializing a clock frequency range of a spread spectrum clocking scheme by which a clock frequency during a data transmission is changed within the clock frequency range;
adjusting the clock frequency range of the first interface device based on how much of the second buffer is filled with data; and
performing a data reception based on the adjusted clock frequency range.