| CPC H04L 5/0051 (2013.01) [H04W 48/08 (2013.01)] | 15 Claims |

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1. An apparatus, comprising:
at least one processor; and
at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform:
determining synchronization signal block(s) that have been transmitted in a serving cell;
receiving group information of tracking reference signals, the group information comprising an indication on those determined synchronization signal block(s) for which a tracking reference signal has been configured in the serving cell, wherein the indication on those determined synchronization signal block(s) for which a tracking reference signal has been configured comprises a synchronization signal block index;
receiving mapping information comprising an indication on how individual tracking reference signal of the tracking reference signals is mapped to a slot structure; and
determining time domain position(s) of tracking reference signal(s) for the apparatus based on the group information and the mapping information.
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