US 12,316,550 B2
Multi-access management service queueing and reordering techniques
Jing Zhu, Portland, OR (US); and Menglei Zhang, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/560,181.
Prior Publication US 2022/0116334 A1, Apr. 14, 2022
Int. Cl. H04L 47/62 (2022.01); H04L 47/34 (2022.01); H04L 49/901 (2022.01); H04W 28/06 (2009.01); H04W 76/15 (2018.01)
CPC H04L 47/622 (2013.01) [H04L 47/34 (2013.01); H04L 49/901 (2013.01); H04W 28/065 (2013.01); H04W 76/15 (2018.02)] 30 Claims
OG exemplary drawing
 
1. A compute node, comprising:
memory circuitry to:
instantiate a ring buffer in a region of the memory circuitry having a fixed size, the ring buffer including a plurality of slots where each slot is assigned a slot index of a plurality of slot indexes, and
instantiate a set of virtual queues, wherein each virtual queue of the set of virtual queues is allocated to one instance of a set of instances and one link of a set of links; and
processor circuitry connected to the memory circuitry, the processor circuitry to execute instructions for multi-queue management, which, when executed are to cause the processor circuitry to:
store a packet to be processed in a subject slot of the plurality of slots, the packet is assigned to a subject instance of the set of instances and a subject link of the set of links, and the subject slot is assigned a subject slot index of the plurality of slot indexes,
store the subject slot index in a subject virtual queue of the set of virtual queues, the subject virtual queue is allocated to the subject instance and the subject link, and
obtain the stored packet from the subject slot using the subject slot index when the packet is scheduled for processing.