| CPC H04L 43/0858 (2013.01) [H04L 41/06 (2013.01); H04L 43/0876 (2013.01)] | 20 Claims |

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1. A processing system comprising:
a master device;
a plurality of destination devices, the plurality of destination devices including a slave device;
an interconnect device connected to the master device and the plurality of destination devices;
a counter device configured to count a number of events of a desired transaction destined for the slave device among the plurality of destination devices based on a unique identifier included in the desired transaction among transactions that are being transmitted over the interconnect device for the plurality of destination devices, the desired transaction including a target request packet; and
a comparator device configured to transmit a reset signal to the counter device in response to a count value of the counter device being invalid,
wherein the counter device is configured to reset the count value to zero in response to receiving the reset signal.
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