| CPC H04L 25/4917 (2013.01) | 20 Claims |

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1. An apparatus comprising:
an encoder circuit configured to:
encode an input data word, having n bits, into respective first and second output data words, each having m bits, wherein m is greater than n, and wherein each of the first and second output data words include a respective first subset of bits and a respective second subset of bits;
identify one of the first subsets of bits that is a complement to one of the second subsets of bits; and
select the identified first and second subsets of bits to form a transmit data word; and
a transmitter circuit configured to serially transmit, using a plurality of voltage levels, a plurality of symbols whose values are based on the transmit data word.
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