| CPC H04L 25/03159 (2013.01) [H04B 1/123 (2013.01); H04L 25/03057 (2013.01); H04L 25/0307 (2013.01); H04L 25/03885 (2013.01); H04L 2025/03356 (2013.01); H04L 2025/03636 (2013.01)] | 20 Claims |

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1. An integrated circuit comprising:
a continuous-time equalizer to receive a signal and to equalize the received signal to produce an equalized signal, wherein the signal exhibits inter-symbol interference (ISI) and the continuous-time equalizer exhibits a gain that is adjustable in response to a control signal;
a first sampler to periodically sample the equalized signal to produce data samples;
a second sampler to sample the equalized signal and thereby produce error samples; and
an adaptation engine to receive the data samples and the error samples, to measure post-cursor ISI of the signal using the data samples and the error samples, and to issue the control signal to the continuous-time equalizer responsive to the measure of the post-cursor ISI.
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