US 12,316,362 B2
Signal receiver and slicer
Hsuan-Ting Ho, Hsinchu (TW); Shih-Hsiung Huang, Hsinchu (TW); and Liang-Wei Huang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Sep. 26, 2022, as Appl. No. 17/952,584.
Claims priority of application No. 110136938 (TW), filed on Oct. 4, 2021.
Prior Publication US 2023/0105538 A1, Apr. 6, 2023
Int. Cl. H04B 1/12 (2006.01)
CPC H04B 1/123 (2013.01) 20 Claims
OG exemplary drawing
 
1. A signal receiver capable of mitigating a static mismatch error of a far-end digital-to-analog converter (far-end DAC), the signal receiver comprising:
an analog-front-end (AFE) circuit configured to generate an analog signal according to a received signal originated from the far-end DAC;
an analog-to-digital converter (ADC) configured to generate a digital signal according to the analog signal;
an equalizer circuit configured to generate an input signal according to the digital signal;
an adjustable slicing circuit configured to determine which level of (N+1) signal levels is corresponding to the input signal according to N slicer levels and thereby generate an output signal, and the adjustable slicing circuit further configured to adjust at least a part of the (N+1) signal levels according to an error signal and adjust at least a part of the N slicer levels, wherein the N is an integer greater than two; and
an error signal generating circuit coupled to the adjustable slicing circuit and configured to generate the error signal according to the input signal and output signal.