US 12,316,360 B2
High performance low complexity memoryless digital pre-distortion
Fei Tong, Cambridge (GB); and Paul Nicholas Fletcher, Cambridge (GB)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 10, 2023, as Appl. No. 18/220,235.
Prior Publication US 2025/0023592 A1, Jan. 16, 2025
Int. Cl. H04B 1/04 (2006.01)
CPC H04B 1/0475 (2013.01) [H04B 2001/045 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of digital memoryless pre-distortion, comprising:
receiving an input digital signal from a signal source;
calculating a look-up table (LUT) address based on a sample of the input signal, a power scale, and a factor to retain a predetermined number of upper bits in the sample;
updating an LUT value associated with the LUT address based on the input signal and an output signal that is output from a power amplifier to a wireless communications channel;
linearizing the output signal with the updated LUT value; and
outputting the output signal to the wireless communications channel,
wherein the steps of updating an LUT value associated with the LUT address and linearizing the output signal with the updated LUT value are repeated until a level of linearization is achieved that meets a pre-defined standard.