US 12,316,349 B2
Iterative decoding technique for correcting DRAM device failures
Joseph M. McCrate, Boise, ID (US); Nevil Gajera, Boise, ID (US); and Mohammed Ebrahim Hargan, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 18, 2024, as Appl. No. 18/608,627.
Application 18/608,627 is a division of application No. 17/896,994, filed on Aug. 26, 2022, granted, now 12,170,531.
Claims priority of provisional application 63/299,394, filed on Jan. 13, 2022.
Prior Publication US 2024/0413842 A1, Dec. 12, 2024
Int. Cl. H03M 13/15 (2006.01); H03M 13/37 (2006.01)
CPC H03M 13/154 (2013.01) [H03M 13/1575 (2013.01); H03M 13/153 (2013.01); H03M 13/1545 (2013.01); H03M 13/373 (2013.01); H03M 13/3746 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An error correction code (ECC) decoder configured to receive data from a memory, comprising:
a syndrome generator configured to receive a codeword from the memory;
an error-location polynomial generator coupled to an output of the syndrome generator; an error value generator; and
an error location generator;
wherein the error value generator and the error location generator are electrically coupled to an output of the error-location polynomial generator;
wherein the error value generator and the error location generator (i) facilitate performing a single decoding attempt to detect random error symbols in a first portion of a word received from one memory component of a plurality of memory components of the memory and (ii) correct the detected random error; and
wherein when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.