US 12,316,342 B2
Product autoencoder for error-correcting via sub-stage processing
Mohammad Vahid Jamali, Ann Arbor, MI (US); Hamid Saber, San Diego, CA (US); Homayoon Hatami, San Diego, CA (US); and Jung Hyun Bae, San Diego, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 9, 2022, as Appl. No. 17/942,064.
Claims priority of provisional application 63/252,027, filed on Oct. 4, 2021.
Prior Publication US 2023/0104143 A1, Apr. 6, 2023
Int. Cl. H03M 13/09 (2006.01); G06N 3/08 (2023.01)
CPC H03M 13/09 (2013.01) [G06N 3/08 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A processing circuit comprising:
a transmitter device; and
an encoder for an (n,k) error correction code, the encoder being configured to:
receive k symbols of original data;
supply the k symbols of original data to a neural product encoder comprising a plurality of M neural encoder stages, a j-th neural encoder stage of the plurality of M neural encoder stages comprising a j-th neural network configured by a j-th plurality of parameters to implement an (nj,kj) error correction code, where nj is a factor of n and kj is a factor of k, and where the j-th neural network comprises a hidden layer comprising Nencj neurons, where Nencj is greater than nj and greater than kj; and
output, to the transmitter device, n symbols of encoded data representing the k symbols of original data encoded by the (n,k) error correction code,
wherein the transmitter device transmits a communication signal comprising the n symbols of encoded data to a receiver device over a communication channel in response to receiving the n symbols of encoded data from the encoder.