US 12,316,341 B2
Cross-coupled capacitive elements in highspeed DAC
Prathamesh Mukund Khatavkar, Dublin (IE); and Roberto Pelliconi, Imola (IT)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Apr. 12, 2023, as Appl. No. 18/133,812.
Prior Publication US 2024/0348261 A1, Oct. 17, 2024
Int. Cl. H03M 1/80 (2006.01); H03M 1/06 (2006.01); H03M 1/68 (2006.01); H03M 1/74 (2006.01); H03M 1/78 (2006.01)
CPC H03M 1/802 (2013.01) [H03M 1/0624 (2013.01); H03M 1/68 (2013.01); H03M 1/747 (2013.01); H03M 1/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital-to-analog converter (DAC) comprising:
an unary cell comprising unary slices coupled to one another in parallel;
an intermediate significant bit (ISB) cell comprising ISB slices coupled to one another in parallel; and
a least significant bit (LSB) cell comprising LSB slices coupled to one another in parallel, the unary cell, the ISB cell, and the LSB cell each being coupled to each other, each of the unary slices comprising a set of cross-coupled capacitive elements, the set of cross-coupled capacitive elements comprising:
first capacitive elements having a first end coupled to a node positioned between a first pair of transistors and a second end coupled to a node positioned between a second pair of transistors; and
second capacitive elements having a first end coupled to a node positioned between a third pair of transistors and a second end coupled to a node positioned between a fourth pair of transistors.