US 12,316,337 B2
Method for synchronizing analogue-digital or digital-analogue converters, and corresponding system
Quentin Beraud-Sudreau, Rives sur Fure (FR); Jérôme Ligozat, Grenoble (FR); Marc Stackler, Hong Kong (CN); and Rémi Laube, Veurey-Voroize (FR)
Assigned to TELEDYNE E2V SEMICONDUCTORS SAS, Saint Egreve (FR)
Appl. No. 18/009,123
Filed by TELEDYNE E2V SEMICONDUCTORS SAS, Saint Egreve (FR)
PCT Filed Jun. 2, 2021, PCT No. PCT/EP2021/064823
§ 371(c)(1), (2) Date Dec. 8, 2022,
PCT Pub. No. WO2021/249848, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. FR2005986 (FR), filed on Jun. 9, 2020.
Prior Publication US 2023/0238975 A1, Jul. 27, 2023
Int. Cl. H03M 1/06 (2006.01)
CPC H03M 1/0624 (2013.01) [H03M 1/0607 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for synchronizing a plurality of analogue-digital or digital-analogue converters (CONV_k), the converters (CONV_k) all being connected to a control unit (UC), and to a clock (CLK) that has a predefined clock period (Tclk), the converters being also chained step-by-step so as to form a chain of converters, each converter (CONV_k) generating an internal synchronization signal (internal_sync_k) configured to supply a time reference on the transmission of data by the converter (CONV_k), the method comprising, for each converter (CONV_k), the following steps:
a) reception of a synchronization signal (sync_in_k) transmitted by the control unit (UC) for the first converter (CONV_1) of the chain, or transmitted by the preceding converter (CONV_k−1) for the other converters of the chain, and transmission of the synchronization signal to a next converter (CONV_k+1) in the form of a so-called output internal signal (sync_out_k), or to the control unit (UC) for the last converter (CONV_N) of the chain;
b) reception, by the next converter (CONV_k+1), of the output internal signal (sync_out_k), and retransmission to the converter (CONV_k) of the output internal signal (sync_out_k) in the form of a so-called check internal signal (sync_in_check_k), except for the last converter of the chain (CONV_N);
c) reception of the check internal signal (sync_in_check_k) by the converter (CONV_k), except for the last converter of the chain (CONV_N);
d) determination of a latency (latCONV_k->CONV_k+1) between the converter and the next converter, except for the last converter (CONV_N) of the chain, by counting, on the same active clock edge, of the clock periods between the transmission of the output internal signal (sync_out_k) and the reception of the check internal signal (sync_in_check_k);
e) computation of an internal offset (ΔCONV_K) to be applied to the internal synchronization signal (internal_sync_k) of each converter (CONV_k), the internal offset being determined as a function of at least a part of the determined latencies.