US 12,316,334 B2
Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection
Venkateswara Pothireddy, McKinney, TX (US); and Bhavesh G. Bhakta, Richardson, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Mar. 31, 2023, as Appl. No. 18/194,049.
Claims priority of provisional application 63/381,976, filed on Nov. 2, 2022.
Prior Publication US 2024/0146315 A1, May 2, 2024
Int. Cl. H03L 7/095 (2006.01); H03L 7/081 (2006.01); H03L 7/089 (2006.01); H03L 7/091 (2006.01)
CPC H03L 7/095 (2013.01) [H03L 7/0812 (2013.01); H03L 7/0891 (2013.01); H03L 7/091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a phase detector configured to produce a first up signal and a first down signal based on a difference between a reference clock and a feedback clock;
a harmonic detector coupled to the phase detector, the harmonic detector configured to produce a second up signal based on the first up signal and whether the harmonic detector detects a harmonic lock between the reference clock and the feedback clock based on a first clock phase and a second clock phase; and
a false lock detector coupled to the phase detector and to the harmonic detector, the false lock detector configured to produce a second down signal based on the first down signal and whether the false lock detector detects a false lock between the reference clock and the feedback clock based on a third clock phase and a fourth clock phase.