US 12,316,332 B2
Digital clean up oscillator
Brent Carlson, Penticton (CA)
Assigned to NATIONAL RESEARCH COUNCIL OF CANADA, Ottawa (CA)
Appl. No. 18/287,746
Filed by NATIONAL RESEARCH COUNCIL OF CANADA, Ottawa (CA)
PCT Filed Apr. 26, 2022, PCT No. PCT/IB2022/053867
§ 371(c)(1), (2) Date Oct. 20, 2023,
PCT Pub. No. WO2022/229844, PCT Pub. Date Nov. 3, 2022.
Claims priority of provisional application 63/188,139, filed on May 13, 2021.
Claims priority of provisional application 63/180,703, filed on Apr. 28, 2021.
Prior Publication US 2024/0187004 A1, Jun. 6, 2024
Int. Cl. H03L 7/093 (2006.01); H03L 7/14 (2006.01)
CPC H03L 7/093 (2013.01) [H03L 7/145 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A digital clean-up oscillator, comprising:
a reference oscillator for generating a high-stability reference clock signal;
a precision digital frequency tracker for receiving the reference clock signal and a noisy clock signal to be cleaned, and in response measuring the frequency of the reference clock signal in the time domain of the noisy clock signal;
a low pass filter for removing any frequency variations from the measured frequency of the reference clock signal on timescales shorter than a phase change interval over which jitter in the clock signal is to be cleaned;
a phase increment calculator for generating a phase increment signal based on the frequency of the reference clock signal measured in the precision digital frequency tracker and filtered by the low pass filter;
a direct digital synthesizer for clocking the phase increment signal with the reference clock signal for generating an output digital phase ramp signal that tracks the frequency of the noisy clock signal with phase wander removed on timescales less than the phase change interval; and
a digital phase to clock converter for converting the digital phase ramp signal to an output jitter-cleaned time domain clock signal frequency locked to the noisy clock signal.