US 12,316,326 B1
Delay circuit
Shishir Kumar, Uttar Pradesh (IN); and Vinay Kumar, Aligarh (IN)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Mar. 1, 2023, as Appl. No. 18/177,111.
Int. Cl. H03K 5/13 (2014.01); G11C 11/16 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/13 (2013.01) [G11C 11/1693 (2013.01); H03K 2005/00202 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit comprising:
a first inverter, having an input, an output, and two power supply connections;
a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and
a ramp generator circuit, electrically coupled to the input of the first inverter, the ramp generator circuit comprising:
a capacitor, electrically coupled to the input of the first inverter;
a second current source electrically coupled to the capacitor; and
a first switching transistor electrically coupled in series between the second current source and the capacitor.