US 12,316,282 B2
Compensation circuit and chip, method, apparatus, storage medium, and electronic device
Jijun Li, Shenzhen (CN); Jingjing Dong, Shenzhen (CN); Guoliang Zhao, Shenzhen (CN); and Zhongyi Chen, Shenzhen (CN)
Assigned to SANECHIPS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/638,498
Filed by SANECHIPS TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed Aug. 26, 2020, PCT No. PCT/CN2020/111361
§ 371(c)(1), (2) Date Feb. 25, 2022,
PCT Pub. No. WO2021/037054, PCT Pub. Date Mar. 4, 2021.
Claims priority of application No. 201910817751.5 (CN), filed on Aug. 30, 2019.
Prior Publication US 2022/0393649 A1, Dec. 8, 2022
Int. Cl. H03F 1/32 (2006.01); H03F 1/30 (2006.01); H03F 3/45 (2006.01)
CPC H03F 1/3205 (2013.01) [H03F 1/301 (2013.01); H03F 3/45475 (2013.01); H03F 2201/3218 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A compensation circuit, comprising:
an analog module comprising at least one input node and at least one output node, wherein each of the at least one input node is configured to receive a corresponding input signal and each of the at least one output node is configured to output a corresponding output signal; and
a linearity compensation module comprising a plurality of transconductance units, wherein the plurality of transconductance units are configured to acquire a first configuration signal and configure a combination of the plurality of transconductance units based on the first configuration signal to provide a compensation signal to the at least one output node to compensate for nonlinear components comprised in the at least one output signal, and said first configuration signal comprises any of the at least one input signal, the at least one output signal, or process signals located at any position between the at least one input node and the at least one output node in the analog module.