US 12,316,279 B2
Amplifier circuit with an envelope enhancement
Chuanzhao Yu, Phoenix, AZ (US); and LiChung Chang, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,205.
Prior Publication US 2022/0416722 A1, Dec. 29, 2022
Int. Cl. H03G 3/20 (2006.01); H03F 1/02 (2006.01); H03F 3/24 (2006.01); H04B 1/40 (2015.01); H03F 1/56 (2006.01)
CPC H03F 1/0216 (2013.01) [H03F 3/245 (2013.01); H04B 1/40 (2013.01); H03F 1/565 (2013.01); H03F 2200/102 (2013.01); H03F 2200/222 (2013.01); H03F 2200/451 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An amplifier circuit comprising:
an amplifier configured to amplify an input signal to provide an output signal;
an amplifier stack comprising a first transistor coupled to the amplifier, the amplifier stack is configured to:
receive the output signal to amplify the output signal;
receive an input control signal to control the first transistor based on an envelope of the input signal;
an amplifier circuit output configured to provide an amplifier output signal based on the input signal received by the amplifier; and
a processor comprising an envelope detector to detect an envelope signal of a received signal, wherein the processor is configured to:
receive the amplifier output signal; and
adjust at least one of an amplitude or a phase of the envelope signal and provide the input control signal based on the adjusted envelope signal.