US 12,315,860 B2
Integrated circuit package for high bandwidth memory
Nam Hoon Kim, San Jose, CA (US); Woon-Seong Kwon, Santa Clara, CA (US); Teckgyu Kang, Saratoga, CA (US); and Yujeong Shim, Cupertino, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Apr. 2, 2024, as Appl. No. 18/624,411.
Application 18/624,411 is a continuation of application No. 17/970,237, filed on Oct. 20, 2022, granted, now 11,990,461.
Application 17/970,237 is a continuation of application No. 17/157,278, filed on Jan. 25, 2021, granted, now 11,488,944, issued on Nov. 1, 2022.
Prior Publication US 2024/0250082 A1, Jul. 25, 2024
Int. Cl. H01L 25/18 (2023.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package comprising:
a substrate;
a silicon interposer positioned on a top surface of the substrate;
one or more logic dice positioned on a top surface of the silicon interposer;
one or more high-bandwidth memory stacks positioned on the substrate and spaced apart from the silicon interposer;
and
a plurality of printed traces formed in the substrate, wherein the logic die is configured to interface the one or more high-bandwidth memory stacks through the plurality of printed traces.