US 12,315,840 B2
Microelectronic assemblies
Shawna M. Liff, Scottsdale, AZ (US); Adel A. Elsherbini, Chandler, AZ (US); and Johanna M. Swan, Scottsdale, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 10, 2022, as Appl. No. 17/885,048.
Application 17/885,048 is a continuation of application No. 17/129,095, filed on Dec. 21, 2020, granted, now 11,469,209.
Application 17/129,095 is a continuation of application No. 16/650,656, granted, now 11,335,665, issued on May 17, 2022, previously published as PCT/US2017/068915, filed on Dec. 29, 2017.
Prior Publication US 2022/0384389 A1, Dec. 1, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/544 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/13 (2013.01); H01L 23/49838 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/06593 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a multi-layer structure including multiple layers of dielectric material, wherein the multi-layer structure includes one or more conductive pathways through the dielectric material;
a first die;
a second die, wherein the second die is between the first die and a surface of the multi-layer structure; and
a third die, wherein the third die is between the first die and the surface of the multi-layer structure;
wherein:
the first die is bonded directly to the second die by first interconnects,
the first die is bonded directly to the third die by second interconnects, and
the third die includes through-substrate vias (TSVs) through a semiconductor substrate of the third die.