| CPC H01L 24/05 (2013.01) [H01L 23/3107 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/48 (2013.01); H01L 25/16 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48227 (2013.01)] | 14 Claims |
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1. A semiconductor package comprising:
a substrate including an upper pad at a top surface of the substrate;
a semiconductor chip on the substrate and including a chip pad at a top surface of the semiconductor chip, wherein the chip pad is electrically connected to the upper pad via a first wire;
a connecting structure on the semiconductor chip and including a connecting pad and a probe pad at a top surface of the connecting structure, wherein the connecting pad is electrically connected to the probe pad via a third wire, and the connecting pad is electrically connected to the upper pad via a second wire;
an encapsulant covering and in direct contact with each of the substrate, the semiconductor chip, and the connecting structure; and
a test terminal on the connecting structure and extending through the encapsulant, the test terminal being electrically connected to and in direct contact with the probe pad of the connecting structure;
wherein the connecting structure electrically interconnects the semiconductor chip and the test terminal via a signal path that passes from the test terminal to the probe pad of the connecting structure, from the probe pad of the connecting structure to the connecting pad of the connecting structure via the third wire, from the connecting pad of the connecting structure to the upper pad of the substrate via the second wire, and from the upper pad of the substrate to the chip pad of the semiconductor chip via the first wire.
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