US 12,315,822 B2
Methods of manufacturing a fan-out panel level semiconductor package
Jeongho Lee, Suwon-si (KR); and Doohwan Lee, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 3, 2024, as Appl. No. 18/403,583.
Application 18/403,583 is a continuation of application No. 17/306,555, filed on May 3, 2021, granted, now 11,901,301.
Claims priority of application No. 10-2020-0078026 (KR), filed on Jun. 25, 2020.
Prior Publication US 2024/0145397 A1, May 2, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/214 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/18161 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, the method comprising:
preparing a frame structure comprising a core portion and a plurality of lower pads under the core portion, wherein a cavity penetrates the core portion;
attaching an adhesive film to each of the plurality of lower pads of the frame structure;
mounting a semiconductor chip in the cavity of the frame structure, wherein the semiconductor chip comprises an active surface on which a plurality of bump pads are arranged and a non-active surface opposite the active surface;
forming a molding member to cover the frame structure and the semiconductor chip;
attaching a carrier substrate to the molding member;
performing a planarization process on a first surface that is exposed by removing the adhesive film, wherein each of the plurality of bump pads of the semiconductor chip has a polygonal column shape or cylindrical shape;
forming a redistribution structure on the first surface that is planarized;
forming an opening portion in the molding member through a second surface that is exposed by removing the carrier substrate; and
attaching an external connection terminal to the redistribution structure.