	US 12,315,820 B2
	Wiring structure including low- and high-density conductive structures
Wen Hung Huang, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/231,768.
Application 18/231,768 is a continuation of application No. 17/157,795, filed on Jan. 25, 2021, granted, now 11,721,634.
Application 17/157,795 is a continuation of application No. 16/399,907, filed on Apr. 30, 2019, granted, now 10,903,169, issued on Jan. 26, 2021.
Prior Publication US 2023/0387034 A1, Nov. 30, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01)

CPC H01L 23/5389 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01)]

18 Claims

1. A wiring structure, comprising:

a low-density conductive structure;

an electronic device embedded in the low-density conductive structure; and

a high-density conductive structure disposed over the low-density conductive structure, spaced apart from the low-density conductive structure by an intermediate layer, and including a bottommost dielectric layer and a bottommost conductive layer, wherein the bottommost dielectric layer has a bottom surface facing the low-density conductive structure, and the bottommost dielectric layer contacts the intermediate layer, wherein the bottommost conductive layer protrudes beyond the bottom surface of the bottommost dielectric layer, wherein an upper surface of the bottommost conductive layer is substantially co-level with a top surface of the intermediate layer, wherein the high-density conductive structure further includes a plurality of high-density circuit layers and an inner via disposed between the plurality of high-density circuit layers, and the inner via tapers away from the low-density conductive structure.