US 12,315,816 B2
Three-dimensional semiconductor memory device including separation structures and sacrificial layers and electronic system including the same
Haemin Lee, Seoul (KR); Byoung-Taek Kim, Seongnam-si (KR); and Hyeonjoo Song, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 9, 2022, as Appl. No. 17/739,583.
Claims priority of application No. 10-2021-0110901 (KR), filed on Aug. 23, 2021.
Prior Publication US 2023/0058328 A1, Feb. 23, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 23/535 (2006.01); H10B 43/40 (2023.01); H10D 88/00 (2025.01)
CPC H01L 23/535 (2013.01) [H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10D 88/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a substrate including a first region and a second region;
a stack structure including a plurality of interlayer dielectric layers and a plurality of gate electrodes that are alternately and repeatedly stacked on the substrate, the stack structure having a stepwise structure on the second region;
a mold structure adjacent to the stack structure on the first region, the mold structure including a plurality of interlayer dielectric layers and a plurality of sacrificial layers that are alternately and repeatedly stacked on the substrate;
a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region; and
a second separation structure crossing the mold structure and extending in the first direction on the first region,
wherein a level of a top surface of the first separation structure is higher than a level of a top surface of the second separation structure.