US 12,315,809 B2
Via for semiconductor device and method
Chia-Pang Kuo, Taoyuan (TW); Chih-Yi Chang, New Taipei (TW); Ming-Hsiao Hsieh, Hsinchu (TW); Wei-Hsiang Chan, Hsinchu (TW); Ya-Lien Lee, Baoshan Township (TW); Chien Chung Huang, Taichung (TW); Chun-Chieh Lin, Taichung (TW); and Hung-Wen Su, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,803.
Application 18/358,803 is a continuation of application No. 17/001,917, filed on Aug. 25, 2020, granted, now 11,810,857.
Prior Publication US 2023/0369224 A1, Nov. 16, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/76804 (2013.01); H01L 21/76846 (2013.01); H01L 21/76877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming an insulating layer over a conductive feature;
forming a metal mask over the insulating layer;
etching the insulating layer using the metal mask to form an opening that exposes a surface of the conductive feature;
selectively depositing an adhesion layer on the exposed surface of the conductive feature;
selectively depositing a sacrificial layer on the adhesion layer;
selectively depositing a barrier layer on surfaces of the insulating layer and the metal mask;
performing a removal process to remove the sacrificial layer, wherein the removal process densifies the barrier layer; and
depositing a conductive fill material in the opening.