US 12,315,769 B2
Build-up package for integrated circuit devices, and methods of making same
Hong Wan Ng, Singapore (SG); Choon Kuan Lee, Singapore (SG); David J. Corisis, Nampa, ID (US); and Chin Hui Chong, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 17, 2022, as Appl. No. 17/843,799.
Application 16/819,486 is a division of application No. 15/145,760, filed on May 3, 2016, granted, now 10,593,607, issued on Mar. 17, 2020.
Application 15/145,760 is a division of application No. 14/307,238, filed on Jun. 17, 2014, granted, now 9,355,994, issued on Oct. 2, 2014.
Application 14/307,238 is a division of application No. 13/182,069, filed on Jul. 13, 2011, granted, now 8,754,537, issued on Jun. 17, 2014.
Application 13/182,069 is a division of application No. 12/753,562, filed on Apr. 2, 2010, abandoned.
Application 12/753,562 is a division of application No. 11/768,413, filed on Jun. 26, 2007, granted, now 7,691,682, issued on Apr. 6, 2010.
Application 17/843,799 is a continuation of application No. 16/819,486, filed on Mar. 16, 2020, granted, now 11,367,667.
Prior Publication US 2023/0005802 A1, Jan. 5, 2023
Int. Cl. H01L 23/18 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 21/78 (2006.01)
CPC H01L 23/18 (2013.01) [H01L 21/56 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/373 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/95 (2013.01); H01L 24/96 (2013.01); H01L 21/7806 (2013.01); H01L 2224/05001 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/14 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/3512 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a die having an active surface;
a bond pad at the active surface, wherein the bond pad has an upper surface, and wherein the upper surface is coplanar with the active surface of the die;
a first layer of insulating material carried by the active surface, the first layer of insulating material including a first opening aligned with the bond pad along a vertical axis perpendicular to the active surface of the die;
a molded body surrounding a lateral perimeter of the die, wherein the molded body includes an extension portion over a portion of the active surface of the die and in contact with a sidewall of the first layer of insulating material;
a second layer of insulating material carried by the first layer of insulating material and the molded body, the second layer of insulating material including a second opening aligned with the first opening along the vertical axis; and
a conductive layer carried by the second layer of insulation material, the conductive layer electrically coupled to the bond pad through the first and second openings.