US 12,315,766 B2
Semiconductor device including spacer layer contacting bit line bottom sidewalls
Kyung Min Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 28, 2021, as Appl. No. 17/563,779.
Claims priority of application No. 10-2021-0106582 (KR), filed on Aug. 12, 2021.
Prior Publication US 2023/0047679 A1, Feb. 16, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/76831 (2013.01); H01L 23/5226 (2013.01); H10B 43/27 (2023.02); H01L 21/31144 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory cell stack comprising dielectric layers and gate electrodes that are alternately stacked with each other, the memory cell stack positioned over a substrate;
a plurality of channel structures each including a channel layer that penetrates the memory cell stack;
a contact-level dielectric layer formed over the plurality of channel structures and including a contact hole that exposes each of the plurality of channel structures;
recessed contact plugs respectively coupled to the channel layer through the contact hole and having an upper surface which is lower than an upper surface of the contact-level dielectric layer;
a bit line-level dielectric layer formed over the recessed contact plugs; and
a plurality of bit lines formed in the bit line-level dielectric layer,
wherein the bit line-level dielectric layer includes a spacer layer in contact with sidewalls of bottom portions of the plurality of bit lines,
wherein the contact-level dielectric layer includes:
a first inter-layer dielectric layer;
a first etch stop layer over the first inter-layer dielectric layer;
a second inter-layer dielectric layer over the first etch stop layer; and
a second etch stop layer over the second inter-layer dielectric layer,
wherein the second etch stop layer is covered by the spacer layer.