US 12,315,738 B2
Method of forming a gate structure including semiconductor material implantation into dummy gate stack
Shih-Hao Lin, Hsinchu (TW); Jui-Lin Chen, Taipei (TW); Hsin-Wen Su, Hsinchu (TW); Kian-Long Lim, Hsinchu (TW); Bwo-Ning Chen, Keelung (TW); and Chih-Hsuan Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 13, 2024, as Appl. No. 18/741,998.
Application 18/741,998 is a continuation of application No. 17/877,221, filed on Jul. 29, 2022, granted, now 12,027,425.
Application 17/877,221 is a continuation of application No. 16/931,717, filed on Jul. 17, 2020, granted, now 11,482,610, issued on Oct. 25, 2022.
Claims priority of provisional application 62/906,158, filed on Sep. 26, 2019.
Prior Publication US 2024/0332089 A1, Oct. 3, 2024
Int. Cl. H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H01L 21/31155 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/792 (2025.01); H10D 62/021 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
18. A method, comprising:
forming a dummy gate stack over a channel region of an active region, the dummy gate stack comprising:
a dummy electrode comprising polysilicon and a necking portion, and
a spacer layer disposed along sidewalls of the dummy electrode;
forming a source/drain feature over a source/drain region of the active region;
depositing a contact etch stop layer (CESL) to interface a sidewall of the spacer layer and a top surface of the source/drain feature;
depositing a dielectric layer over the CESL;
planarizing the dielectric layer to expose the spacer layer and the dummy electrode;
after the planarizing, implanting germanium into the dielectric layer, the spacer layer and the dummy electrode;
after the implanting, annealing the dummy electrode to widen the necking portion; and
after the annealing, replacing the dummy gate stack with a metal gate stack,
wherein the metal gate stack comprises titanium aluminum.