US 12,315,730 B2
Semiconductor devices with metal intercalated high-k capping
Chandrashekhar Prakash Savant, Hsinchu (TW); Kin Shun Chong, Hsinchu (TW); Tien-Wei Yu, Hsinchu (TW); and Chia-Ming Tsai, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 10, 2022, as Appl. No. 17/741,270.
Claims priority of provisional application 63/283,092, filed on Nov. 24, 2021.
Prior Publication US 2023/0162983 A1, May 25, 2023
Int. Cl. H01L 21/28 (2025.01); H10D 64/66 (2025.01)
CPC H01L 21/28088 (2013.01) [H10D 64/667 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium;
forming a metal nitride layer over the high-k gate dielectric layer;
performing a first treatment to the structure using a metal-containing gas;
after the performing of the first treatment, depositing a silicon layer over the metal nitride layer; and
after the depositing of the silicon layer, annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer, wherein the metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.