US 12,315,726 B2
Semiconductor device and method
Ching-Yu Chang, Taipei (TW); Jung-Hau Shiu, New Taipei (TW); Jen Hung Wang, Hsinchu (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 5, 2024, as Appl. No. 18/595,554.
Application 18/595,554 is a continuation of application No. 17/377,813, filed on Jul. 16, 2021, granted, now 11,948,798.
Application 17/377,813 is a continuation of application No. 16/583,949, filed on Sep. 26, 2019, granted, now 11,069,528, issued on Jul. 20, 2021.
Claims priority of provisional application 62/753,184, filed on Oct. 31, 2018.
Prior Publication US 2024/0249942 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/033 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/0331 (2013.01) [H01L 21/02167 (2013.01); H01L 21/02211 (2013.01); H01L 21/02214 (2013.01); H01L 21/0228 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing an integrated circuit, the method comprising:
forming a first patterned mask over a target layer, the first patterned mask having a first pattern and a second pattern;
forming a multi-layer gap-filling material into an opening between the first pattern and the second pattern of the first patterned mask, the multi-layer gap-filling material extending above top surfaces of the first patterned mask;
removing portions of the multi-layer gap-filling material above the top surfaces of the first patterned mask; and
patterning the target layer to form a patterned target layer, patterning the target layer using remaining portions of the multi-layer gap-filling material as a mask.